Many of today's semiconductor packages are formed using so-called flip-chip technology. In such packaging, a semiconductor die is coupled to an underlying package substrate using a solder to connect a bump on the die with a bump on the package substrate.
As process technologies move away from lead-based solders to lead-free solders, after elevated temperatures at which reflow is performed, sufficient stress can be present in the package to cause delamination of dielectric layers such as a carbon doped oxide (CDO) layer of the semiconductor die. Such stress can occur as a result of coefficient terminal expansion (CTE) mismatches. While one solution to this problem implements a so-called no-flow under film (NUF) process, where an underflow material is allowed to gel and distribute stress to an entire die surface before cooling of the resulting joined package and die to room temperature, excessive costs and time is required and furthermore, expensive tooling is needed for each such die size to enable this process.